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preliminary cy14b101la, cy14b101na 1 mbit (128k x 8/64k x 16) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-42879 rev. *b revised january 29, 2009 features 20 ns, 25 ns, and 45 ns access times internally organized as 128k x 8 (cy14b101la) or 64k x 16 (cy14b101na) hands off automatic store on power down with only a small capacitor store to quantumtrap ? nonvolatile elements initiated by software, device pin, or autostore ? on power down recall to sram initiated by software or power up infinite read, write, and recall cycles 200,000 store cycles to quantumtrap 20 year data retention single 3v +20% to -10% operation commercial and industrial temperatures 48-ball fbga, 44-pin tsop - ii, 48-pin ssop, and 32-pin soic packages pb-free and rohs compliance functional description the cypress cy14b101la/cy14b101na is a fast static ram, with a nonvolatile element in each memory cell. the memory is organized as 128k bytes of 8 bits each or 64k words of 16 bits each. the embedded nonvolatile elements incorporate quantumtrap technology, producing the world?s most reliable nonvolatile memory. the sram provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. 67$7,&5$0 $55$< ; 5 2 : ' ( & 2 ' ( 5 &2/801,2 &2/801'(& , 1 3 8 7 % 8 ) ) ( 5 6 32:(5 &21752/ 6725(5(&$// &21752/ 4xdwuxp7uds ; 6725( 5(&$// 9 && 9 &$3 +6% $ $ $ $ $ $ $ 62)7:$5( '(7(&7 $ $ 2( &( :( %+( %/( $ $ $ $ $ $ $ $ $ $ '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 logic block diagram [1, 2, 3] note 1. address a 0 - a 16 for x8 configuration and address a 0 - a 15 for x16 configuration. 2. data dq 0 - dq 7 for x8 configuration and data dq 0 - dq 15 for x16 configuration. 3. bhe and ble are applicable for x16 configuration only. [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 2 of 25 pinouts figure 1. pin diagram - 48 fbga figure 2. pin diagram - 44 pin tsop ii we v cc a 11 a 10 v cap a 6 a 0 a 3 ce nc nc dq 0 a 4 a 5 nc dq 2 dq 3 nc v ss a 9 a 8 oe v ss a 7 nc nc nc nc a 2 a 1 nc v cc dq 4 nc dq 5 dq 6 nc dq 7 nc a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h a 16 nc nc dq 1 48-fbga (not to scale) top view (x8) [6] [7] we v cc a 11 a 10 v cap a 6 a 0 a 3 ce dq 10 dq 8 dq 9 a 4 a 5 dq 13 dq 12 dq 14 dq 15 v ss a 9 a 8 oe v ss a 7 dq 0 bhe nc nc a 2 a 1 ble v cc dq 2 dq 1 dq 3 dq 4 dq 5 dq 6 dq 7 a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h nc nc nc dq 11 48-fbga (not to scale) top view (x16) [6] [7] [4] [5] [4] [5] nc a 8 nc nc v ss dq 6 dq 5 dq 4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) a 10 nc we dq 7 hsb nc v ss v cc v cap nc (x8) [6] [7] v ss dq 6 dq 5 dq 4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 ble a 9 ce a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 11 a 10 a 14 bhe oe a 15 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) we dq 7 a 0 v ss v cc dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 v cap (x16) 44-tsop ii (x8) 44-tsop ii (x16) [8] [4] [5] [4] [5] notes 4. address expansion for 2 mbit. nc pin not connected to die. 5. address expansion for 4 mbit. nc pin not connected to die. 6. address expansion for 8 mbit. nc pin not connected to die. 7. address expansion for 16 mbit. nc pin not connected to die. 8. hsb pin is not available in 44-tsop ii (x16) package. [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 3 of 25 figure 3. pin diagram - 48-pin ssop and 32-pin soic table 1. pin definitions pin name i/o type description a 0 ? a 16 input address inputs used to select one of the 131,072 bytes of the nvsram for x8 configuration. a 0 ? a 15 address inputs used to select one of the 65,536 words of the nvsram for x16 configuration. dq 0 ? dq 7 input/output bidirectional data i/o lines for x8 configuration . used as input or output lines depending on operation. dq 0 ? dq 15 bidirectional data i/o lines for x16 configuration . used as input or output lines depending on operation. we input write enable input, active low . when the chip is enabled and we is low, data on the i/o pins is written to the specific address location. ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. i/o pins are tri- stated on deasserting oe high. bhe input byte high enable, active low . controls dq 15 - dq 8 . ble input byte low enable, active low . controls dq 7 - dq 0 . v ss ground ground for the device . must be connected to the ground of the system. v cc power supply power supply inputs to the device . 3.0v +20%, ?10% hsb [8] input/output hardware store busy (hsb ) . when low this output indicates that a hardware store is in progress. when pulled low external to the chip it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). after each store operation hsb is driven high for short time with standard output high current. v cap power supply autostore capacitor . supplies power to the nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connect . this pin is not connected to the die. pinouts (continued) nc a 8 nc nc v ss dq6 dq5 dq4 v cc a 13 dq3 a 12 dq2 dq1 dq0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 top view (not to scale) a 10 nc we dq7 hsb int v ss v cc v cap nc 45 46 47 48 nc nc nc nc 48-ssop [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 4 of 25 device operation the cy14b101la/cy14b101na nvsram is made up of two functional components paired in the same physical cell. they are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to the sram (the recall operation). using this unique arch itecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14b101la/cy14b101na supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 200k store operations. refer to the truth table for sram operations on page 15 for a complete description of read and write modes. sram read the cy14b101la/cy14b101na performs a read cycle when ce and oe are low and we and hsb are high. the address specified on pins a 0-16 or a 0-15 determines which of the 131,072 data bytes or 65,536 words of 16 bits each are accessed. byte enables (bhe , ble ) determine which bytes are enabled to the output, in the case of 16-bit word s. when the read is initiated by an address transition, the output s are valid after a delay of t aa (read cycle 1). if the r ead is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data output repeatedly responds to address changes within the t aa access time without the need fo r transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the data on the common i/o pins dq 0?15 are written into the memory if the data is valid t sd before the end of a we -controlled write or before the end of a ce -controlled write. the byte enable inputs (bhe , ble ) determine which bytes are written, in the case of 16-bit words. keep oe high during the entire write cycle to avoi d data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b101la/cy14b101na stores data to the nvsram using one of the following three storage operations: hardware store activated by hsb; software store activated by an address sequence; autostore on device power down. the autostore operation is a uni que feature of quantumtrap technology and is enabled by default on the cy14b101la/cy14b101na. during a normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 4 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 7 for the size of v cap . the voltage on the v cap pin is driven to v cc by a regulator on the chip. place a pull up on we to hold it inactive during power up. this pull up is only effective if the we signal is tri-state during power up. many mpus tri-state their controls on power up. this must be verified when using the pull up. when the nvsram comes out of power-on-recall, the mpu must be active or the we held inactive until the mpu comes out of reset. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiat ed store cycles are performed regardless of whether a write operation has taken place. the hsb signal is monitored by the syst em to detect if an autostore cycle is in progress. figure 4. autostore mode hardware store operation the cy14b101la/cy14b101na provides the hsb [8] pin to control and acknowledge the store operations. use the hsb pin to request a hardware store cycle. when the hsb pin is driven low, the cy14b101la/cy14b101na conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the cy14b101la/cy14b101na continues sram operations for t delay . however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. if the write latch is not set, hsb is not driven low by the cy14b101la/cy14b101n a, but any sram read/write cycles are inhibited until hsb is returned high by mpu or another external source. 0.1uf vcc 10kohm v cap vcc we v cap v ss [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 5 of 25 during any store operation, rega rdless of how it is initiated, the cy14b101la/cy14b101na c ontinues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation, the cy14b101la/cy14b101na remains disabled until the hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power up) during power up or after any low power condition (v cc preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 6 of 25 preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore is reenabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or reenabled, a manual store operation (hardware or software) must be issued to save the autostore state through subsequent power down cycles. the part comes from the factory with autostore enabled. data protection the cy14b101la/cy14b101na protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc is less than v switch . if the cy14b101la/cy14b101na is in a write mode (both ce and we are low) at power up, after a recall or store, the write is inhibited until the sram is enabled after t lzhsb (hsb to output active). this protects against in advertent writes during power up or brown out conditions. noise considerations refer to cy application note an1064 . l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [10] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [10] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [10] table 2. mode selection (continued) ce we oe , bhe , ble [3] a 15 - a 0 [9] mode i/o power [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 7 of 25 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c maximum accumulated storage time: at 150 c ambient temperature ........................1000h at 85 c ambient temperature..................... 20 years ambient temperature wit h power applied.. ?55 c to +150 c supply voltage on v cc relative to gnd ..........?0.5v to 4.1v voltage applied to outputs in high-z state?0.5v to v cc + 0.5v input voltage.............................................?0.5v to vcc+0.5v transient voltage (<20 ns) on any pin to ground potential .................. ?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount pb soldering temperature (3 seconds) .......................................... +260 c dc output current (1 output at a time, 1s dura tion)......15 ma static discharge voltage....... ........... ............ ............ > 2001v (per mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial ?40 c to +85 c 2.7v to 3.6v dc electrical characteristics over the operating range (v cc = 2.7v to 3.6v) parameter description test conditions min max unit i cc1 average v cc current t rc = 20 ns t rc = 25 ns t rc = 45 ns values obtained without output loads (i out = 0 ma) commercial 65 65 50 ma ma ma industrial 70 70 52 ma ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max average current for duration t store 10 ma i cc3 [11] average v cc current at t rc = 200 ns, 3v, 25c typical all i/p cycling at cmos levels. values obtained without output loads (i out = 0 ma) 35 ma i cc4 average v cap current during autostore cycle all inputs don?t care, v cc = max average current for duration t store 5ma i sb v cc standby current ce > (v cc ? 0.2v). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz 5ma i ix [12] input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 +1 a input leakage current (for hsb ) v cc = max, v ss < v in < v cc ?100 +1 a i oz off-state output leakage current v cc = max, v ss < v out < v cc , ce or oe > v ih or bhe /ble > v ih or we < v il ?1 +1 a v ih input high voltage 2.0 v cc +0.5 v v il input low voltage v ss ?0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap [13] storage capacitor between v cap pin and v ss , 5v rated 61 180 f notes 11. typical conditions for the active current shown on the dc el ectrical characteristics are average values at 25c (room temper ature), and v cc = 3v. not 100% tested. 12. the hsb pin has i out = -2 ua for v oh of 2.4v when both active high and low drivers ar e disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. 13. v cap (storage capacitor) nominal value is 68 uf. [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 8 of 25 ac test conditions input pulse levels.................................................... 0v to 3v input rise and fall times (10% - 90%)........................ < 3 ns input and output timing reference levels.................... 1.5v data retention and endurance parameter description min unit data r data retention 20 years nv c nonvolatile store operations 200 k capacitance parameter [14] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 7pf c out output capacitance 7 pf thermal resistance parameter [14] description test conditions 48-fbga 48-ssop 44-tsop ii 32-soic unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 28.82 tbd 31.11 tbd c/w jc thermal resistance (junction to case) 7.84 tbd 5.56 tbd c/w figure 5. ac test loads 3.0v output 5 pf r1 r2 789 3.0v output 30 pf r1 r2 789 for tri-state specs 577 577 14. these parameters are guaranteed by design and are not tested. [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 9 of 25 ac switching characteristics parameters description 20 ns 25 ns 45 ns unit cypress parameters alt parameters min max min max min max sram read cycle t ace t acs chip enable access time 20 25 45 ns t rc [15] t rc read cycle time 20 25 45 ns t aa [16] t aa address access time 20 25 45 ns t doe t oe output enable to data valid 10 12 20 ns t oha [16] t oh output hold after address change 3 3 3 ns t lzce [14, 17] t lz chip enable to output active 3 3 3 ns t hzce [14, 17] t hz chip disable to output inactive 8 10 15 ns t lzoe [14, 17] t olz output enable to output active 0 0 0 ns t hzoe [14, 17] t ohz output disable to output inactive 8 10 15 ns t pu [14] t pa chip enable to power active 0 0 0 ns t pd [14] t ps chip disable to power standby 20 25 45 ns t dbe[ [14] - byte enable to data valid 10 12 20 ns t lzbe [14] - byte enable to output active 0 0 0 ns t hzbe [14] - byte disable to output inactive 8 10 15 ns sram write cycle t wc t wc write cycle time 20 25 45 ns t pwe t wp write pulse width 15 20 30 ns t sce t cw chip enable to end of write 15 20 30 ns t sd t dw data setup to end of write 8 10 15 ns t hd t dh data hold after end of write 0 0 0 ns t aw t aw address setup to end of write 15 20 30 ns t sa t as address setup to start of write 0 0 0 ns t ha t wr address hold after end of write 0 0 0 ns t hzwe [14, 17,18] t wz write enable to output disable 8 10 15 ns t lzwe [14, 17] t ow output active after end of write 3 3 3 ns t bw - byte enable to end of write 15 20 30 ns switching waveforms figure 6. sram read cycle #1: address controlled [15, 16, 19] address data output address valid previous data valid output data valid t rc t aa t oha notes 15. we must be high during sram read cycles. 16. device is continuously selected with ce , oe and bhe / ble low. 17. measured 200 mv from steady state output voltage. 18. if we is low when ce goes low, the outputs remain in the high impedance state. 19. hsb must remain high during read and write cycles. [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 10 of 25 note 21. ce or we must be > v ih during address transitions. figure 7. sram read cycle #2: ce and oe controlled [3, 15, 19] figure 8. sram write cycle #1: we controlled [3, 18, 19, 21] address valid address data output output data valid standby active high impedance ce oe bhe, ble i cc t hzce t rc t ace t aa t lzce t doe t lzoe t dbe t lzbe t pu t pd t hzbe t hzoe data output data input input data valid high impedance address valid address previous data t wc t sce t ha t bw t aw t pwe t sa t sd t hd t hzwe t lzwe we bhe, ble ce [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 11 of 25 figure 9. sram write cycle #2: ce controlled [3, 18, 19, 21] figure 10. sram write cycle #3: bhe and ble controlled [3, 18, 19, 21] data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sa t sce t ha t bw t pwe data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sce t sa t bw t ha t aw t pwe [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 12 of 25 autostore/power up recall parameters description 20 ns 25 ns 45 ns unit min max min max min max t hrecall [27] power up recall duration 20 20 20 ms t store [23] store cycle duration 8 8 8 ms t delay [24] time allowed to complete sram cycle 20 25 25 ns v switch low voltage trigger level 2.65 2.65 2.65 v t vccrise vcc rise time 150 150 150 s v hdis [14] hsb output driver disable voltage 1.9 1.9 1.9 v t lzhsb hsb to output active time 5 5 5 s t hhhd hsb high active time 500 500 500 ns switching waveforms figure 11. autostore or power up recall [27] v switch v hdis v vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power- up recall read & write inhibited ( rwi ) power-up recall read & write brown out autostore power-up recall read & write power down autostore note 23 note 23 note 26 notes 22. t hrecall starts from the time v cc rises above v switch. 23. if an sram write has not taken place since the last nonvolatile cycle, no au tostore or hardware store takes place. 24. on a hardware store, software store / recall, autostore enable / disable and autostore initiation, sram operation continues to be enabled for time t delay . 25. read and wr ite cycles are ignored during store, recall, and while vcc is below v switch. 26. hsb pin is driven high to vcc only by internal 100kohm resistor, hsb driver is disabled. [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 13 of 25 software controlled store/recall cycle parameters [27, 28] description 20 ns 25 ns 45 ns unit min max min max min max t rc store/recall initiation cycle time 20 25 45 ns t sa address setup time 0 0 0 ns t cw clock pulse width 15 20 30 ns t ha address hold time 0 0 0 ns t recall recall duration 200 200 200 s switching waveforms figure 12. ce and oe controlled software store/recall cycle [28] figure 13. autostore enable / disable cycle t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb(storeonly) dq (data) rwi t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss notes 27. the software sequence is clocked with ce controlled or oe controlled reads. 28. the six consecutive addr esses must be read in the order listed in table 2 on page 5. we must be high during a ll six consecutive cycles. [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 14 of 25 hardware store cycle parameters description 20ns 25ns 45ns unit min max min max min max t dhsb hsb to output active time when write latch not set 20 25 25 ns t phsb hardware store pulse width 15 15 15 ns t ss [29, 30] soft sequence processing time 100 100 100 s switching waveforms figure 14. hardware store cycle [23] figure 15. soft sequence processing [29, 30] t phsb t phsb t delay t dhsb t delay t store t hhhd t lzhsb write latch set write latch not set hsb (in) hsb (out) dq (data out) rwi hsb (in) hsb (out) rwi hsb pin is driven high to v cc only by internal sram is disabled as long as hsb (in) is driven low. hsb driver is disabled t dhsb 100kohm resistor, address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw notes 29. this is the amount of time it takes to take action on a soft sequence command. vcc power must re main high to effectively reg ister command. 30. commands such as store and recall lock out io until operation is complete which further increases this time. see the specifi c command. [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 15 of 25 truth table for sram operations hsb must remain high for sram operations. table 3. truth table for x8 configuration ce we oe inputs/outputs [2] mode power h x x high z deselect/power down standby l h l data out (dq 0 ?dq 7 ); read active l h h high z output disabled active l l x data in (dq 0 ?dq 7 ); write active table 4. truth table for x16 configuration ce we oe bhe ble inputs/outputs [2] mode power h x x x x high-z deselect/power down standby l x x h h high-z output disabled active l h l l l data out (dq 0 ?dq 15 ) read active l h l h l data out (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z read active l h l l h data out (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z read active l h h l l high-z output disabled active l h h h l high-z output disabled active l h h l h high-z output disabled active l l x l l data in (dq 0 ?dq 15 ) write active l l x h l data in (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z write active l l x l h data in (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z write active [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 16 of 25 ordering information speed (ns) ordering code package diagram package type operating range 20 cy14b101la-zs20xct 51-85087 44-pin tsop ii commercial cy14b101la-zs20xc 51-85087 44-pin tsop ii cy14b101la-ba20xct 51-85128 48-ball fbga cy14b101la-ba20xc 51-85128 48-ball fbga cy14b101la-sp20xct 51-85061 48-pin ssop cy14b101la-sp20xc 51-85061 48-pin ssop cy14b101la-sz20xct 51-85127 32-pin soic cy14b101la-sz20xc 51-85127 32-pin soic cy14b101na-zs20xct 51-85087 44-pin tsop ii cy14b101na-zs20xc 51-85087 44-pin tsop ii cy14b101na-ba20xct 51-85128 48-ball fbga cy14b101na-ba20xc 51-85128 48-ball fbga cy14b101la-zs20xit 51-85087 44-pin tsop ii industrial cy14b101la-zs20xi 51-85087 44-pin tsop ii cy14b101la-ba20xit 51-85128 48-ball fbga cy14b101la-ba20xi 51-85128 48-ball fbga cy14b101la-sp20xit 51-85061 48-pin ssop cy14b101la-sp20xi 51-85061 48-pin ssop cy14b101la-sz20xit 51-85127 32-pin soic cy14b101la-sz20xi 51-85127 32-pin soic cy14b101na-zs20xit 51-85087 44-pin tsop ii cy14b101na-zs20xi 51-85087 44-pin tsop ii cy14b101na-ba20xit 51-85128 48-ball fbga cy14b101na-ba20xi 51-85128 48-ball fbga [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 17 of 25 25 cy14b101la-zs25xct 51-85087 44-pin tsop ii commercial cy14b101la-zs25xc 51-85087 44-pin tsop ii cy14b101la-ba25xct 51-85128 48-ball fbga cy14b101la-ba25xc 51-85128 48-ball fbga cy14b101la-sp25xct 51-85061 48-pin ssop cy14b101la-sp25xc 51-85061 48-pin ssop cy14b101la-sz25xct 51-85127 32-pin soic cy14b101la-sz25xc 51-85127 32-pin soic cy14b101na-zs25xct 51-85087 44-pin tsop ii cy14b101na-zs25xc 51-85087 44-pin tsop ii cy14b101na-ba25xct 51-85128 48-ball fbga cy14b101na-ba25xc 51-85128 48-ball fbga cy14b101la-zs25xit 51-85087 44-pin tsop ii industrial cy14b101la-zs25xi 51-85087 44-pin tsop ii cy14b101la-ba25xit 51-85128 48-ball fbga cy14b101la-ba25xi 51-85128 48-ball fbga cy14b101la-sp25xit 51-85061 48-pin ssop cy14b101la-sp25xi 51-85061 48-pin ssop cy14b101la-sz25xit 51-85127 32-pin soic cy14b101la-sz25xi 51-85127 32-pin soic cy14b101na-zs25xit 51-85087 44-pin tsop ii cy14b101na-zs25xi 51-85087 44-pin tsop ii cy14b101na-ba25xit 51-85128 48-ball fbga cy14b101na-ba25xi 51-85128 48-ball fbga ordering information (continued) speed (ns) ordering code package diagram package type operating range [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 18 of 25 45 cy14b101la-zs45xct 51-85087 44-pin tsop ii commercial cy14b101la-zs45xc 51-85087 44-pin tsop ii CY14B101LA-BA45XCT 51-85128 48-ball fbga cy14b101la-ba45xc 51-85128 48-ball fbga cy14b101la-sp45xct 51-85061 48-pin ssop cy14b101la-sp45xc 51-85061 48-pin ssop cy14b101la-sz45xct 51-85127 32-pin soic cy14b101la-sz45xc 51-85127 32-pin soic cy14b101na-zs45xct 51-85087 44-pin tsop ii cy14b101na-zs45xc 51-85087 44-pin tsop ii cy14b101na-ba45xct 51-85128 48-ball fbga cy14b101na-ba45xc 51-85128 48-ball fbga cy14b101la-zs45xit 51-85087 44-pin tsop ii industrial cy14b101la-zs45xi 51-85087 44-pin tsop ii cy14b101la-ba45xit 51-85128 48-ball fbga cy14b101la-ba45xi 51-85128 48-ball fbga cy14b101la-sp45xit 51-85061 48-pin ssop cy14b101la-sp45xi 51-85061 48-pin ssop cy14b101la-sz45xit 51-85127 32-pin soic cy14b101la-sz45xi 51-85127 32-pin soic cy14b101na-zs45xit 51-85087 44-pin tsop ii cy14b101na-zs45xi 51-85087 44-pin tsop ii cy14b101na-ba45xit 51-85128 48-ball fbga cy14b101na-ba45xi 51-85128 48-ball fbga all parts are pb-free. the above table contains preliminary info rmation. please contact your local cypress sales representative for availability of these parts. ordering information (continued) speed (ns) ordering code package diagram package type operating range [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 19 of 25 part numbering nomenclature option: t - tape & reel blank - std. speed: 20 - 20 ns 25 - 25 ns data bus: l - x8 n - x16 density: 101 - 1 mb voltage: b - 3.0v cypress cy 14 b 101l a-zs 20 x c t nvsram 14 - autostore + software store + hardware store temperature: c - commercial (0 to 70c) i - industrial (?40 to 85c) pb-free package: ba - 48 fbga zs - tsop ii 45 - 45 ns sp - 48 ssop sz - 32 soic die revision: blank: no rev a - 1 st rev [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 20 of 25 package diagrams figure 16. 44-pin tsop ii (51-85087) max min. dimension in mm (inch) 11.938 (0.470) plane seating pin 1 i.d. 44 1 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) ejector pin r g o k e a x s 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) base plane 0.10 (.004) 22 23 top view bottom view 51-85087-*a [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 21 of 25 figure 17. 48-ball fbga - 6 mm x 10 mm x 1.2 mm (51-85128) package diagrams (continued) a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.20 max c seating plane 0.530.05 0.25 c 0.15 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 10.000.10 a 10.000.10 6.000.10 b 1.875 2.625 0.36 51-85128-d [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 22 of 25 figure 18. 48-pin ssop (51-85061) package diagrams (continued) 51-85061 *c [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 23 of 25 figure 19. 32-pin soic (51-85127) package diagrams (continued) [+] feedback
preliminary cy14b101la, cy14b101na document #: 001-42879 rev. *b page 24 of 25 document history page document title: cy14b101la/cy14b101na 1 mbit (128k x 8/64k x 16) nvsram document number: 001-42879 rev. ecn no. submission date orig. of change description of change ** 2050747 see ecn unc/pyrs new data sheet *a 2607447 11/14/2008 gvch/aesa remo ved 15 ns access speed updated ?features? updated logic block diagram added footnote 1 2, 3 and 7 pin definition: updated we , hsb and nc pin description page 4: updated sram read, sram wr ite, autostore operation description updated figure 4 page 4: updated hardware store oper ation and hardware recall (power up)description page 4: updated software store and software recall description footnote 1 and 11 referenced for mode selection table added footnote 11 updated footnote 9 and 10 page 6: updated data protection description maximum ratings:added max. accumulated storage time changed output short circuit current parameter name to dc output current changed i cc2 from 6ma to 10ma changed i cc3 from 15ma to 35ma changed i cc4 from 6ma to 5ma changed i sb from 3ma to 5ma added i ix for hsb updated i cc1, i cc3, i sb and i oz test conditions changed v cap voltage min value from 68uf to 61uf added v cap voltage max value to 180uf updated footnote 12 and 13 added footnote 14 added data retention and endurance table added thermal resistance value to 48-pin fbga and 44-pin tsop ii packages updated input rise and fall time in ac test conditions referenced footnote 17 to t oha parameter updated all switching waveforms updated footnote 17 added footnote 20 added figure 10 (sram write cycle:bhe and ble controlled) changed t store max value from 12.5ms to 8ms updated t delay value added v hdis , t hhhd and t lzhsb parameters updated footnote 24 added footnote 26 and 27 software controlled store/recall table: changed t as to t sa changed t ghax to t ha changed t ha value from 1ns to 0 ns added figure 13 added t dhsb parameter changed t hlhx to t phsb updated t ss from 70us to 100us added truth table for sram operations updated ordering information and part numbering nomenclature *b 2654484 02/05/09 gvch/pyrs changed the data sheet from advance information to preliminary referenced note 15 to parameters t lzce , t hzce , t lzoe, t hzoe, t lzwe and t hzwe updated figure 12 [+] feedback
document #: 001-42879 rev. *b revised january 29, 2009 page 25 of 25 autostore and quantumtrap are registered trademarks of cypress semiconductor corporation. all products and company names mentio ned in this document are the trademarks of their respective holders. preliminary cy14b101la, cy14b101na ? cypress semiconductor corporation, 2008-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb [+] feedback

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